View DS2175_671445.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS2175 t1/cept elastic store DS2175 022798 1/12 features ? rate buffer for t1 and cept transmission systems ? synchronizes looptimed and system timed data streams on frame boundaries ? ideal for t1 (1.544 mhz) to cept (2.048 mhz), cept to t1 interfaces ? supports parallel and serial backplanes ? buffer depth is 2 frames ? comprehensive onchip aslipo control logic slips occur only on frame boundaries outputs report slip occurrences and direction align feature allows buffer to be recentered at any time buffer depth easily monitored ? compatible with ds2180a t1 and ds2181a cept transceivers ? industrial temperature range of 40 c to +85 c avail- able, designated DS2175n pin assignment slip aln s/p 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vdd sysclk sser smsync sfsync schclk sclksel rclksel rclk rser rmsync fsd vss 16pin dip (300 mil) 16pin soic (300 mil) description the DS2175 is a lowpower cmos elasticstore memory optimized for use in primary rate telecommu- nications transmission equipment. the device serves as a synchronizing element between async data streams and is compatible with north american (t11.544 mhz) and european (cept2.048 mhz) rate networks. the chip has several flexible operating modes which eliminate support logic and hardware cur- rently required to interconnect parallel or serial tdm backplanes. application areas include digital trunks, drop and insert equipment, digital crossconnects (dacs), private network equipment and pabxto computer interfaces such as dmi and cpi.
DS2175 022798 2/12 DS2175 block diagram figure 1 slip v ss v dd aln s/p pcm buffer slip logic system controller receive controller rser rclk rmsync rclksel sser sfsync sysclk smsync schclk sclksel fsd
DS2175 022798 3/12 pin description table 1 pin symbol type description 1 rclksel i receive clock select . tie to v ss for 1.544 mhz applications, to v dd for 2.048 mhz. 2 rclk i receive clock . 1.544 or 2.048 mhz data clock. 3 rser i receive serial data . sampled on falling edge of rclk. 4 rmsync i receive multifram sync . rising edge establishes receive side frame and multiframe boundaries. 5 fsd o frame slip direction . state indicates direction of last slip; latched on slip occurrence. 6 slip o frame slip . active low, open collector output. held low for 65 sysclk cycles when a slip occurs. 7 aln i align . recenters buffer on next system side frame boundary when forced low; negative edgetriggered. 8 v ss signal ground . 0.0 volts 9 sclksel i system clock select . tie to v ss for 1.544 mhz applications, to v dd for 2.048 mhz. 10 s/p i serial/parallel select . tie to v ss for parallel backplane applications, to v dd for serial. 11 schclk o system channel clock . transitions high on channel boundaries; useful for serial to parallel conversion of channel data. 12 sfsync i system frame sync . rising edge establishes system side frame bound- aries. 13 smsync o system multiframe sync . slipcompensated multiframe output; used with rmsync to monitor depth of store real time. 14 sser o system serial data . updated on rising edge of sysclk. 15 sysclk i system clock . 1.544 or 2.048 mhz data clock. 16 v dd positive supply . 5.0 volts.
DS2175 022798 4/12 pcm buffer the DS2175 utilizes a 2frame buffer to synchronize in- coming pcm data to the system backplane clock. buff- er depth is modedependent; 2.048 mhz to 2.048 mhz applications utilize 64 bytes of buffer memory, while all other modes are supported by 48 bytes. the buffer samples data at rser on the falling edge of rclk. output data appears at sser and is updated on the ris- ing edge of sysclk. the buffer depth is constantly monitored by onboard contention logic; a aslipo occurs when the buffer is completely emptied or filled. slips au- tomatically recenter the buffer to a oneframe depth and always occur on frame boundaries. data format data is presented to, and output from, the elastic store in a aframedo format. a rising edge at rmsync and sfsync establishes frame boundaries for the receive and system sides. north american (t1) frames contain 24 data channels of 8 bits each and an fbit (193 bits total). european (cept) frames contain 32 data chan- nels (256 bits). the frame rate of both systems is 8 khz. rmsync and sfsync do not require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment. internal counters will then maintain the frame alignment and may be reinforced by the next rising edge at rmsync and/or sfsync. slip correction capability the 2frame buffer depth is adequate for tcarrier and cept applications where short term jitter synchroniza- tion, rather than correction of significant frequency dif- ferences, is required. the DS2175 provides an ideal balance between total delay (less than 250 microse- conds at its full depth) and slip correction capability. buffer recentering many applications require that the buffer be recentered during system powerup and/or initialization. forcing aln low recenters the buffer on the occurrence of the next frame sync boundary. a slip will occur during this recentering if the buffer depth is adjusted. if the depth is presently optimum, no adjustment (slip) occurs. slip reporting slip is held low for 65 sysclk cycles when a slip oc- curs. slip is an activelow, open collector output. fsd indicates slip direction. when low (buffer empty) a frame of data was arepeatedo at sser during the pre- vious slip. when high (buffer full), a frame of data was adeletedo. fsd is updated at every slip occurrence. buffer depth monitoring smsync is a system side output pulse which indicates system side multiframe boundaries. the distance be- tween rising edges of rmsync and smsync indi- cates the current buffer depth. impending slip condi- tions may be determined by monitoring rmsync and smsync real time. smsync is held high for 65 sysclk periods. clock select receive and system side clock frequencies are inde- pendently selectable by inputs rclksel and sclksel. 1.544 mhz is selected when rclksel (sclksel) = 0; 2.048 mhz is selected when rclksel (sclksel) = 1. in 1.544 mhz (receive) to 1.544 mhz (system) applications, the fbit position is passed through the receive buffer and presented at sser im- mediately after the rising edge of the system side frame sync. the fbit position is forced to 1 in 2.048 mhz to 1.544 mhz applications. no fbit position exists in 2.048 mhz system side applications. parallel compatibility the DS2175 is compatible with parallel and serial back- planes. channel 1 data appears at sser after a rising edge at sfsync (serial applications, s/p = 1). the de- vice utilizes a lookahead circuit in parallel applications (s/p = 0), and presents data 8 clocks early as shown in figures 4 and 5. converting sser to a parallel format requires an hc595 shift register.
DS2175 022798 5/12 receive side timing (rclk = 1.544 mhz) figure 2 rclk rmsync rser lsb msb lsb f msb lsb channel 24 channel 1 receive side timing (rclk = 2.048 mhz) figure 3 rser 1 rclk rmsync lsb msb lsb msb lsb channel 32 channel 1 notes: 1. all channel data is passed through the elastic store in 2.048 mhz system side applications (sclksel = 1); 2. data in channels >24 is ignored in 1.544 mhz system side applications (sclksel = 0). system multiframe boundary timing (sysclk = 1.544 mhz) figure 4 sysclk lsb msb lsb f msb lsb channel 24 channel 1 lsb msb lsb f msb lsb channel 1 channel 2 sfsync smsync schclk sser 1 (s/p =0) sser 1 (s/p =1)
DS2175 022798 6/12 notes: 1. in 1.544 mhz receive side applications (rclksel=0), the fbit position contains fbit data extracted from the data stream at rser. the fbit position is forced to a1o in 2.048 mhz receive side applications (rclksel=1). 2. in 2.048 mhz receive side applications (rclksel=1), the ebit position is forced to a1o and data in channels >24 is ignored. system multiframe boundary timing (sysclk = 2.048 mhz) figure 5 sysclk lsb msb lsb msb lsb channel 1 channel 2 sfsync smsync schclk sser 1 (s/p =0) sser 1 (s/p =1) lsb msb lsb msb lsb channel 32 channel 1 notes: 1. in 2.048 mhz receive side applications (rclksel=1), all channel data is passed through the elastic store. 2. in 1.544 mhz receive side applications (rclksel=0), all channel data is passed through the elastic store, except the fbit position which is ignored. data in channels >24 on the system side is forced to all ones.
DS2175 022798 7/12 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v dd +0.3 v logic 0 v il 0.3 +0.8 v supply v dd 4.5 5.5 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf dc electrical characteristics (0 c to 70 c; v dd = 5v 10%) parameter symbol min typ max units notes supply current i dd 9 16 ma 1, 2 input leakage i il 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma 3 output current @ 0.4v i ol +4.0 ma 4 notes: 1. sysclk = rclk = 2.048 mhz 2. outputs open 3. all outputs except slip , which is open collector 4. all outputs
DS2175 022798 8/12 ac electrical characteristics (0 c to 70 c; v dd = 5v 10%) parameter symbol min typ max units notes rclk period t rclk 200 ns rclk, sysclk rise and fall times t r , t f 20 ns rclk pulse width t rwh , t rwl 100 ns sysclk pulse width t swh , t swl 100 ns sysclk period t sysclk 200 ns rmsync setup to rclk falling t sc 20 t rwh 5 ns sfsync setup to sysclk falling t sc 20 t swh 5 ns rmsync, sfsync, aln pulse width t pw 50 ns rser setup to rclk falling t sd 50 ns rser hold from rclk falling t hd 50 ns propagation delay sysclk to sser t pvd 75 ns propagation delay sysclk to smsync high t pss 75 ns propagation delay sysclk or rclk to slip low, fsd low/ high t ps 100 ns aln setup to sfsync rising t sr 500 ns notes: 1. measured at v ih =2.0v, v il 0.8v, and 10 ns maximum rise and fall times. 2. output load capacitance = 100 pf.
aln , sigh slip t r t f t sysclk t swh t swl t sc t pw t pvd t ps sysclk sfsync sser t pss t pw t sr t psf smsync DS2175 022798 9/12 receive ac timing diagram figure 6 slip t r t f t rclk t rwh t rwl t s t pw t pvd t ps t sd t hd rclk rmsync rser system ac timing diagram figure 7
DS2175 022798 10/12 DS2175 t1/cept elastic store dim min max 16pin pkg a in. b in. c in. d in. e in. f in. g in. h in j in. k in. 0.740 0.780 0.240 0.260 0.120 0.140 0.300 0.325 0.015 0.040 0.120 0.140 0.090 0.110 0.290 0.420 0.008 0.012 0.015 0.021 9 16 8 1 a b j 7 equal spaces at .100 .010 (tna) kg c e f d h
DS2175 022798 11/12 DS2175s t1/cept elastic store dim min max 16pin pkg a in. b in. c in. e in. f in. g in. h in j in. k in. 0.402 0.412 0.290 0.300 0.089 0.095 0.004 0.012 0.094 0.105 0.398 0.416 0.009 0.013 0.013 0.019 h j g c f 6 typ a k 18 16 9 e b l in. 0.016 0.040 l 0.050 bsc
DS2175 022798 12/12 data sheet revision summary the following represent the key differences between 04/19/95 and 06/13/97 version of the DS2175 data sheet. please review this summary carefully. 1. sync/clock relationship in timing diagram

▲Up To Search▲

Price & Availability of DS2175

	To Download DS2175 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .